In semi-conductor memory components a distinction is made between so-called functional memory components (i.e. PLAs, PALs, etc.), and so-called tab memory components, i.e. ROM components (ROM=Read Only Memory), and RAM components (RAM=Random Access Memory).
A RAM component is a memory device in which data is stored under a specified address, from which the data can be read out again.
Because a RAM component needs to be provided with as many storage cells as possible, it becomes important for the creation of these cells to be kept as simple as possible. With so-called SRAMs (SRAM=Static Random Access Memory) the individual memory cells for instance consist of a few, e.g. six transistors; and in so-called DRAMs (DRAM=Dynamic Random Access Memory) of only a single suitably controlled capacitance (i.e. the gate source capacitance of a MOSFET), with which in form of a charge one bit at a time can be stored. This charge only persists for a short period of time, which means that a so-called “refresh” must be per-formed regularly, i.e. ca. every 64 ms.
With DRAM components one can distinguish between so-called SDR-DRAMs, and so-called DDR-DRAMs and/or DDR2-DRAMs. In SDR-DRAMs (SDR-DRAM=Single Date Rate DRAM) the data in the component is always only relayed with the ascending pulse flank of a corresponding pulse (clock) signal (or alternatively only with the descending pulse flank).
With DDR-DRAM components (DDR-DRAM=Double Data Rate DRAM), or with their corresponding successive standard “DDR2” components, the data is relayed with the ascending flank of a corresponding pulse (clock) signal as well as with the descending flank of the corresponding pulse (clock) signal.
This means that data is relayed more frequently and/or faster in a DDR-DRAM (and/or a DDR2-DRAM), in particular twice as frequently and/or twice as fast, than in an SDR-DRAM.
Due to their increased integration density and functionality, the design of RAMs, especially DRAM components, has become ever more complex.
Due to this complexity of the components, a structured—i.e. a “top down”, “bottom up” or similar conventional approach to design—has become necessary.
In a top down approach for instance, the design of a particular component starts at a relatively high level of abstraction whereafter the relevant design is progressively refined at increasingly lower levels of abstraction (e.g. according to the procedure suggested by D. Gajski in “Introduction to Silicon Compilation”, Reading (Mass.), (illustrated in FIG. 4)—from a functional point of view—by starting at a “systems level”, proceeding via an “algorithm register transfer and/or logic level” to a “circuit level” etc., or—from a structural point of view—by starting at a “CPU—and/or memory level”, proceeding via a sub-system module gate level to a “transistor level”, etc.), until finally the mask data required for manufacturing the components is obtained.
Thereby appropriate tests and/or simulations corresponding with each design stage take place (at every level of abstraction); in case of faults the design result must then be modified, and/or the corresponding design step repeated, or the design started anew at a higher level.
This procedure is able to ensure—despite the increased component complexity due to higher integration density and increased functionality—that the designed component operates in a fault-free fashion.
The complexity of DRAM components may for example be even further increased when a particular component is made “variably configurable” during its design (i.e. optionally configurable as an SDR-DRAM, DDR-DRAM or DDR2-DRAM, and/or as a component with 8 or 16 bit data output, and/or as a component with or without special optional features, i.e. with or without power-saving mode, etc.).
The actual configuration of the DRAM component (i.e. as SDR, DDR or DDR2-DRAM, etc.) is then done by means of so-called fuses or bonds—according to the customer's needs—after the DRAM components have been manufactured.
In this way the customer's needs can be met shortly before the component is dispatched, i.e. it can be custom configured by means of the above fuses or bonds.
At the same time, the circuitry not required for the configuration that is finally installed (but still required for the non-installed configurations) create further increased component complexity.